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Micrel, Inc.
3.3V, 500MHz 1:22 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR
Precision Edge(R) SY89823L Precision Edge(R)
SY89823L
FEATURES
s 22 differential HSTL (low-voltage swing) output pairs s HSTL outputs drive 50 to ground with no offset s s s s s s s
Precision Edge(R)
voltage 3.3V core supply, 1.8V output supply for reduced power LVPECL and HSTL inputs Low part-to-part skew (200ps max.) Low pin-to-pin skew (50ps max.) Triple-buffered output enable (OE) -40C to +85C temperature range Available in a 64-pin EPAD-TQFP
DESCRIPTION
The SY89823L is a high-performance bus clock driver with 22 differential High-Speed Transceiver Logic (HSTL), 1.5V compatible output pairs. The device is designed for use in low-voltage (3.3V/ 1.8V) applications that require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. The input is multiplexed from either HSTL or Low-Voltage PositiveEmitter-Coupled Logic (LVPECL) by the CLK_SEL pin. The Output Enable (OE) is synchronous and triple-buffered so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any potential of generating a runt clock pulse when the device is enabled/disabled, as can occur with an asynchronous control. The triple-buffering feature provides a threeclock delay from the time the OE input is asserted/de-asserted to when the clock appears at the outputs. The SY89823L features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.), performance previously unachievable in a standard product having such a high number of outputs. The SY89823L is available in a single, space-saving package, enabling a lower overall cost solution. All support documentation can be found on Micrel's web site at: www.micrel.com.
APPLICATIONS
s High-performance PCs s Workstations s Parallel processor-based systems s Other high-performance computing s Communications
LOGIC SYMBOL
CLK_SEL HSTL_CLK /HSTL_CLK
TRUTH TABLE
OE(1) 0
0 22 22 Q0 - Q21 /Q0 - /Q21
CLK_SEL 0 1 0 1
Q0-Q21 LOW LOW HSTL_CLK LVPECL_CLK
/Q0-/Q21 HIGH HIGH /HSTL_CLK /LVPECL_CLK
0 1 1
Note:
EN ENABLE LOGIC
LVPECL_CLK
1
/LVPECL_CLK
1. The output enable (OE) signal is synchronized with the low level of the HSTL_CLK and LVPECL_CLK signal.
OE
TYPICAL PERFORMANCE
900
OUTPUT AMPLITUDE (mV)
Output Amplitude vs. Frequency
800 700 600 500 400 300 200 100 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Precision Edge is a registered trademark of Micrel, Inc. M9999-091908 hbwhelp@micrel.com or (408) 955-1690
OUTPUT FREQUENCY (GHz)
Rev.: D Amendment: /0
1
Issue Date: September 2008
Micrel, Inc.
Precision Edge(R) SY89823L
PACKAGE/ORDERING INFORMATION
VCCO Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 VCCO
Ordering Information(1)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCCO Q7 /Q7 Q8 /Q8 Q9 /Q9 Q10 /Q10 Q11 /Q11 Q12 /Q12 Q13 /Q13 VCCO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VCCO NC NC VCCI HSTL_CLK /HSTL_CLK CLK_SEL LVPECL_CLK /LVPECL_CLK GND OE NC NC /Q21 Q21 VCCO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VCCO /Q20 Q20 /Q19 Q19 /Q18 Q18 /Q17 Q17 /Q16 Q16 /Q15 Q15 /Q14 Q14 VCCO
Part Number SY89823LHC SY89823LHCTR(2) SY89823LHZ(3) SY89823LHZTR(2, 3) SY89823LHI SY89823LHITR(2, 3) SY89823LHY(3) SY89823LHYTR(2, 3)
Package Type H64-1 H64-1 H64-1 H64-1 H64-1 H64-1 H64-1 H64-1
Operating Range Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial
Package Marking SY89823LHC SY89823LHC SY89823LHZ with Pb-Free bar-line indicator SY89823LHZ with Pb-Free bar-line indicator SY89823LHI with Pb-Free bar-line indicator SY89823LHI with Pb-Free bar-line indicator SY89823LHY with Pb-Free bar-line indicator SY89823LHY with Pb-Free bar-line indicator
Lead Finish Sn-Pb Sn-Pb Pb-Free Matte-Sn Pb-Free Matte-Sn Sn-Pb Sn-Pb Pb-Free Matte-Sn Pb-Free Matte-Sn
64-Pin EPAD-TQFP (H64-1)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC electricals only. 2. Tape and Reel. 3. Pb-Free package recommended for new designs.
PIN DESCRIPTION
Pin Number
5, 6
Pin Name
HSTL_CLK, /HSTL_CLK LVPECL_CLK, /LVPECL_CLK CLK_SEL OE
Type
HSTL Input LVPECL Input LVTTL Input LVTTL Input
Pin Function
Differential clock input selected by CLK_SEL. Can be left floating if not selected. Floating input, if selected, produces an indeterminate output. HSTL input signal requires external termination 50 to GND. Differential clock input selected by CLK_SEL. Can be left floating. Floating input, if selected, produces a LOW at the output. Requires external termination. 75k pull-up. Selects HSTL_CLK input when LOW and LVPECL_CLK output when HIGH. 11k pull-up. Default condition selects LVPECL_CLK if left open. Enable input synchronized internally to prevent glitching of the Q0-Q21 and /Q0-/Q21 outputs. Must be a minimum of three clock periods wide if synchronous with the CLK inputs and must meet the tS and tH requirements (refer to "AC Electrical Characteristics" section). If asynchronous, must be a minimum of four clock periods wide. 11k pull-up. Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated with 50 to GND. Q0-Q21 outputs are static LOW when OE = LOW. Unused output pairs may be left floating. Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated with 50 to GND. /Q0-/Q21 outputs are static HIGH when OE = LOW. Unused output pairs may be left floating. Core VCC connected to 3.3V supply. Bypass with 0.1F in parallel with Power 0.01F low ESR capacitors as close to VCCI pins as possible. Output Buffer VCC connected to 1.8V supply. Bypass with 0.1F in parallel with 0.01F low ESR capacitors as close to VCCO pin as possible. All VCCO pins should be connected together on the PCB. Ground pin and exposed pad must be connected to the same ground plane. No Connect.
8, 9 7 11
63, 61, 59, 57, 55, 53 51, 47, 45, 43, 41, 39 37, 35, 31, 29, 27 25, 23, 21, 19, 15 62, 60, 58, 56, 54, 52 50, 46, 44, 42, 40, 38 36, 34, 30, 28, 26 24, 22, 20, 18, 14 4 1, 16, 17, 32, 33, 48, 49, 64 10 2, 3, 12, 13
Q0-Q21
HSTL Output
/Q0-/Q21
HSTL Output
VCCI VCCO
VCC Core VCC Output Power
GND, Exposed Pad NC
M9999-091908 hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge(R) SY89823L
Absolute Maximum Ratings(1)
Supply Voltage (VIN) ..................................... -0.5V to VCCI VCC Pin Potential to Ground Pin VCCI, VCCO ........................................................... -0.5V to +4.0V DC Output Current, Output HIGH (IOUT) .................. -50mA Lead Temperature (soldering, 20 sec.) ..................... 260C Storage Temperature (TS) ....................... -65C to +150C
Operating Ratings(2)
Supply Voltage VCCI .................................................................. +3.15V to +3.45V VCCO ..................................................................... +1.6V to +2.0V Ambient Temperature (TA) ......................... -40C to +85C Package Thermal Resistance(3) EPAD-TQFP (JA) with Die attach soldered to GND Still-Air ............................................................. 23C/W 200lfpm ............................................................ 18C/W 500lfpm ............................................................ 15C/W with Die attach NOT soldered to GND Still-Air ............................................................. 44C/W 200lfpm ............................................................ 36C/W 500lfpm ............................................................ 30C/W EPAD-TQFP (JC) .............................................. 4.3C/W
DC ELECTRICAL CHARACTERISTICS(4)
Power Supply TA = -40C to +85C, unless otherwise stated. Symbol VCCI VCCO ICCI Parameter VCC Core VCC Output ICC Core Max VCC, no load Condition Min 3.15 1.6 -- Typ 3.3 1.8 115 Max 3.45 2.0 170 Units V V mA
HSTL VCCI = 3.3V 5%; VCCO = 1.8V 10%; RL = 50 to GND; TA = -40C to +85C, unless otherwise stated. Symbol VOH VOL VIH VIL VX IIH IIL Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Crossover Voltage Input HIGH Current Input LOW Current Condition Min 1.0 0.2 VX +0.1 -0.3 0.68 +20 -- Typ -- -- -- -- -- -- -- Max 1.2 0.4 1.6 VX -0.1 0.9 -350 -500 Units V V V V V A A
LVPECL VCCI = 3.3V 5%; VCCO = 1.8V 10%; TA = -40C to +85C, unless otherwise stated. Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Condition Min Max Units V V A A VCCI - 1.165 VCCI - 0.880 VCCI - 1.810 VCCI - 1.475 -- 0.5 +150 --
Notes: 1. Permanent device damage may occur if the ratings in the "Absolute Maximum Ratings" section are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Valid for 4-layer board. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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Micrel, Inc.
Precision Edge(R) SY89823L
DC ELECTRICAL CHARACTERISTICS(5)
LVCMOS/LVTTL VCCI = 3.3V 5%; VCCO = 1.8V 10%; TA = -40C to +85C, unless otherwise stated. Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Condition Min 2.0 -- +20 -- Typ -- -- -- -- Max -- 0.8 -250 -600 Units V V A A
AC ELECTRICAL CHARACTERISTICS(6)
VCCI = 3.3V 5%; VCCO = 1.8V 10%; All outputs loaded with 50 to GND; TA = -40C to +85C, unless otherwise stated. Symbol fMAX tpd tSKEW tSKPP Vpp VCMR tS tH tr, tf tJITTER Parameter Maximum Operating Frequency Propagation Delay CLK-to-Q SEL-to-Q Within-Device Skew Part-to-Part Skew Minimum Input Swing LVPECL_CLK Common Mode Range LVPECL_CLK OE Set-Up Time OE Hold Time Output Rise/Fall Time (20% - 80%) Cycle-to-Cycle Jitter Note 13 Condition VOUT 450mV Note 7 Note 7 Note 8 Note 9 Note 10 Note 11 Note 12 Min 500 0.8 0.8 -- -- 600 -1.5 1.0 0.5 300 Typ -- -- 1.2 -- -- -- -- -- -- -- Max -- 1.3 1.7 50 200 -- -0.4 -- -- 700 1 Units MHz ns ns ps ps mV V ns ns ps psRMS
Notes: 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. High-frequency AC-parameters are guaranteed by design and characterization. 7. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. 8. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. 9. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. 10. The VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. 11. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP(min). The lower end of the CMR range varies 1:1 with VCCI. The VCMR(min) will be fixed at 3.3V - |VCMR(min)|. 12. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures outputs remain disabled during the next clock cycle. OE LOW-to-HIGH transition enables normal operation of the next input clock. 13. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn-Tn-1 where T is the time between rising edges of the output signal.
M9999-091908 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
Precision Edge(R) SY89823L
TIMING DIAGRAMS
Assert Latency CLK
De-assert Latency
tS OE
tH
Q0 - Q21
Notes: 1. The OE input signal must be a minimum of 3 clock periods with width. 2. The internal enable is asserted and de-asserted on the falling edge of clock. 3. The internal enable occurs 2.5 clock cycles (plus the set-up time of OE with the rising edge of clock) after the rising edge of the external OE. 4. If OE does not meet the tS of tH specifications as in asynchronous applications, OE must be a minimum of 4 clock periods in width.
HSTL_CLK, LVPECL_CLK /HSTL_CLK, /LVPECL_CLK tPD Q0 - Q21 /Q0 - /Q21
CLK_SEL tPD Q0 - Q21 /Q0 - /Q21 tPD
M9999-091908 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
Precision Edge(R) SY89823L
TYPICAL OPERATING CHARACTERISTICS
VCCI = 3.6V, VCCO = 2.0V, TA = 25C, unless otherwise stated.
200MHz Output
/Q /Q
400MHz Output
Output Swing (100mV/div.)
Output Swing (100mV/div.)
Q Q
TIME (700ps/div)
TIME (500ps/div)
500MHz Output
/Q
Output Swing (100mV/div.)
Q
TIME (500ps/div)
M9999-091908 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
Precision Edge(R) SY89823L
LVPECL/HSTL INPUTS
VCC VCC
LVPECL_CLK 75k 75k
HSTL_CLK /HSTL_CLK Clamp
/LVPECL_CLK
GND
GND
Figure 1. Simplified LVPECL Input Stage
Figure 2. Simplified HSTL Input Stage
HSTL OUTPUTS
QOUT 1.6V QOUT - /QOUT
QOUT 800mV /QOUT
/QOUT
Figure 3. Output Driver Signal Levels (Single-Ended)
Figure 4. Output Driver Signal Levels (Differential)
RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION
Part Number SY89809L SY89808L Function 3.3V 1:9 High-Performance, Low-Voltage Bus Clock Driver 3.3V, 500MHz, 1:9 Differential HSTL (1.5V) Fanout Buffer Translator Exposed Pad Application Note HBW Solutions MIC3775 New Products and Applications 750mA Cap Low-Voltage Low-Dropout Regulator Data Sheet Link http://www.micrel.com/product-info/products/sy89809l.shtml http://www.micrel.com/product-info/products/sy89808l.shtml http://www.amkor.com/products/notes_papers/epad.pdf http://www.micrel.com/product-info/products/solutions.shtml http://www.micrel.com/product-info/products/mic3775.shtml
M9999-091908 hbwhelp@micrel.com or (408) 955-1690
7
Micrel, Inc.
Precision Edge(R) SY89823L
64-PIN EPAD-TQFP (DIE UP) (H64-1)
+0.05 -0.05 +0.002 -0.002
+0.05 -0.05 +0.012 -0.012
+0.03 -0.03 +0.012 -0.012
+0.15 -0.15 +0.006 -0.006
+0.05 -0.05 +0.002 -0.002
Rev. 02
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 64-Pin EPAD-TQFP Package (Always solder or equivalent the exposed pad to the PCB) Package Notes: 1. Package meets Level 2 qualification. 2. All parts are dry-packaged before shipment. 3. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
USA
+ 1 (408) 944-0800
FAX
+ 1 (408) 944-0970
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. M9999-091908 hbwhelp@micrel.com or (408) 955-1690
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